| 摘要 |
PURPOSE:To decrease the number of circuit elements of high speed motion and the power consumption and to make the operation of the titled circuit speedy by providing N-pieces of pattern detecting circuits in parallel operation each of which operates with 1/N of the frequency of the clock signal of a reception signal. CONSTITUTION:The high-speed input signal data is converted to N-pieces of parallel low speed signals by a series-parallel convertor circuit 1 based on the output clock from a frequency divider 2. The N-pieces parallel low speed signals are inputted to an N-line shift register 3 that shifts with the 1/N clock. Among the outputs of the register 3, N groups of the M bits each of which is shifted one bit from each other are taken out at the high speed side and respectively inputted to the N-pieces of pattern detecting circuits 4-1-4-n, and the relative value in relation to a reference pattern is respectively calculated. Because the pattern detection is executed at every N-piece bit of the input signal, the detecting circuits 4-1-4-n operate at a 1/N speed, and the detection pulse outputted after the pattern detection has an N-bit width. |
