Separately addressable memory arrays in a multiple array semiconductor chip

摘要

A circuit for inhibiting data transfer to addressed memory locations in a plurality of arrays on a semiconductor chip includes an arbitration circuit (68) that distinguishes between separate inhibit signal inputs on dedicated &upbar& C terminals and multiplexed inhibit signals on the input of an I/O buffer (66). The arbitration circuit (68) controls the enable circuits (64) for transferring data from the I/O buffer (66) to memory arrays (10), (12), (14) and (16). Separate inhibit signals allow multiple arrays to share common row and column decoders and maintain separate read/write capability.