| 摘要 |
An M-bit binary counter is disclosed having M sequentially ascending binary value stages, the first stage being the lowest significant bit. In accordance with the invention, each stage above the least significant bit stage has a subsequent value decoder which has the function of determining the effect of lower order carry bits on higher order stages with a minimum of signal delay. The decoder includes the feature of using natural threshold FET devices in a transfer gate configuration to perform logical AND functions so as to minimize gate delays in decoding a carry condition for higher order stages. A selective up-counting or down-counting function is also disclosed.
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