| 摘要 |
The invention relates to an interruption mechanism for a data processing system. The interruption mechanism comprises an execution processing unit (1) and a memory unit (2). The execution processing unit (1) includes a basic processor status storage (13), an extended processor status storage (14), current and new processor status block pointer storages (11, 12), and an interruption control section (17). Following the acceptance of interruption request, the interruption mechanism is sequentially operated by a plurality of steps. The interruption mechanism improves the performance of the execution processing unit (1). |
