| 摘要 |
PURPOSE:To improve the degree of circuit integration by writing '1', '0' from a bit line to two full-size dummy cells connected to bit line pair by a dummy word line controller and equalizing the both before the word line is driven thereby avoiding the restriction of the degree of circuit integration of the memory due to the size of the dummy cell. CONSTITUTION:A dummy word line controller 11 is connected to the end of a dummy word line DWL and bit line information corresponding to a dummy cell 4 to be selected is written on a dummy cell 4 not selected by using a dummy set signal phiDS. In this case, the dummy capacitor included in the dummy cell 4 has the same capacitance as that of a memory capacitor Cs. Then the levels '1', '0' written on the two dummy capacitors are equalized by the dummy equalizing signal phiDE before the word line (dummy word line) is driven to form a reference electric charge being one-half signal electric charge in the memory cell.
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