| 摘要 |
PURPOSE:To decrease a hardware quantity and at the same time to eliminate a processing time delay by detecting the storing action of a storage instruction executed in advance after an instruction is prefetched and indicating the prefetch invalidity to an instruction prefetching mechanism according to a specific output. CONSTITUTION:A gate circuit 15 compares the contents of a register 6 which holds the next instruction address with the contents of an address comparing register 10 which holds an indicated address. While a selecting gate circuit 16 compares the contents of a register 7 which holds the load/store address of a subject memory with the contents of the register 6. Then a comparator 11 compares the contents of both circuits 15 and 16 with each other. Based on the result of comparison of the comparator 11, an address comparison control circuit 12 produces an address comparison satisfying signal 18. Thus the prefetch invalidating signal can be produced as long as the coincidence is secured between both contents of registers 6 and 7.
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