| 摘要 |
PURPOSE:To prevent a transient current and to improve the noise immunity performance by sending the inverted output of a coincident output only when two inputs are not coincident to an intermediate output of a series connection while not changing its output value. CONSTITUTION:Only when two inputs X, Y are dissident, both channel transfer gates 470 are turned on by an exclusive OR circuit 450 and the 3rd CMOS inverter 460 and the 1st and 2nd CMOS inverters 414, 417 constitute the latch structure, then a complete logical '1' or '0' is outputted as an output C. That is, when the two inputs X, Y of the device are logical '0', '1' or logical '1', '0' respectively, the node F goes to the floating state, but in such a case only, both the channel transfer gates 470 are turned on and the output of the 2nd CMOS inverter 417 is sent to the node F, then when the output C is close com paratively to, e.g., logical '1' (or logical '0'), the output of the 2nd CMOS inverter 417 approaches comparatively logical '0' (or '1').
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