| 摘要 |
The timepiece comprises an oscillator (1), a frequency divider (2), a control circuit (3), a stepping motor (4), a seconds hand (5), a circuit (7) for detecting steps missed by the motor, an up-down counter (15) having a capacity N, and a flip-flop (16). At each missed step the detecting circuit (7) generates a tally pulse (S7) which increments the counter (15). The latter is also decremented by periodic pulses appearing on the B output of the frequency divider (2). When a cell supplying the timepiece is nearly exhausted, the number of steps missed per unit of time is high and the counter (15) is, on balance, incremented. When passing from state N-1 to state N the counter issues on its Qh output a pulse that causes the Q output of the flip-flop (16) to go high. The control circuit (3) produces, in response to this high state of the flip-flop, a signal warning of the imminent end of the cell's life in the form of an irregular motion of the seconds hand (5). Otherwise, when the cell is still good, the number of missed steps is low and the counter (15) is decremented. When passing from state 1 to state 0 the counter issues on its Qb output a pulse that causes the Q output of the flip-flop (16) to go low, thereby stopping the warning signal.
|
