FILLER BANK CONTROL CIRCUIT FOR SYNCHRONOUS FIFO QUEUES AND OTHER MEMORY DEVICES

摘要

In described examples, apparatus (200) includes a controller (270) and logic circuitry (275). The controller (270) is configured to generate multiple single-bit logic values. Each single-bit logic value has one of: (a) a first value indicating that a data packet has been written into a memory (210); and (b) a second value indicating that a data packet has been read from the memory (210). The logic circuitry (275) is configured to serially stack the single-bit logic values. The apparatus (200) could further include a shift memory bank (280) configured to store the single-bit logic values. The logic circuitry (275) can be configured to serially stack the single-bit logic values in the shift memory bank (280). For example, the logic circuitry (275) can be configured to shift the single-bit logic values in the shift memory bank (280) in different directions and insert one single -bit logic value into the memory bank at different ends depending on whether the one logic value has the first or second value.