| 摘要 |
PURPOSE:To improve the operating efficiency of a processor having high processing speed in a reception side by transmitting plural packets repeatedly and stopping transmitting the packet at every time when all processors receive the same packet completely and adding another packet to transmit them. CONSTITUTION:A transmission-side processor 1 transmits plural packets, whose number is equal to the number of flip flops 51-54 of a reception-side processor 4, repeatedly to a data bus. When all flip flops (for example, 51) of individual reception-side processors are set, a control signal goes to '1' through an OR circuit 2, and it is detected thereby that the pertinent packet is received by all reception-side processors, and transmission of the packet is stopped. Data to be transferred next is obtained and is added to another packet as the new packet to start transmission. Thus, the queuing time is shortened in processors having high processing speed in the reception side to improve the operating efficiency.
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