发明名称 FREQUENCY DIVISION CIRCUIT
摘要 PURPOSE:To obtain a frequency division waveform with a duty factor of 50% by using a clock for one of two flip-flops and an inverted clock for the other so as to trigger them and inhibiting the trigger input of the other flip-flop depending on the output side of one flip-flop. CONSTITUTION:A clock and a positive logic output of the 2nd FF 4 are inputted to the 1st AND 1 and the 1st trigger appears at the output. The 1st FF 2 is inverted by the trigger to open the 2nd AND 3. Then an inverted clock appears at the output of the 2nd AND 3 to trigger the 2nd FF 4. When the 2nd FF 4 is inverted, the 1st AND 1 closes the gate. Thus, the 2nd clock is not inputted to the 1st FF 2. The two FFs make count while inhibiting alternately the clock input as above. The 3rd FF 5 is set/reset by a negative logic output of the 1st FF 2 and the 2nd FF 4 to form a frequency division waveform of a 50% duty factor.
申请公布号 JPS61287322(A) 申请公布日期 1986.12.17
申请号 JP19850128832 申请日期 1985.06.13
申请人 MITSUBISHI ELECTRIC CORP 发明人 ITO TAKASHI
分类号 H03K23/58;H03K23/00 主分类号 H03K23/58
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