| 摘要 |
PURPOSE:To improve the speed of a multi-stage connection counter by forecasting in advance a carry when an output of the least significant counter reaches a value before the final value, outputting an enable-signal immediately after the output reaches the final value at the next clock and applying carry to decrease the delay. CONSTITUTION:A decode circuit 13 outputting an enable-signal when the output of the least significant digit counter is a value before the final value, a flip-flop 14 using a clock to latch the enable-signal and an enable-control circuit 15 generating the enable-signal when the loaded value is the final value at loading and cleared at a value other than the final value are provided between the least significant counter 11 and its high-order counter 12. Thus, the operation of a multi-stage connection counter is quickened with very simple constitution. |
