发明名称 INTERRUPT PROCESSING CIRCUIT
摘要 PURPOSE:To reduce the number of control lines and to simplify the constitution by using a data bus to report information, which indicates an interrupt factor whose interrupt should be accepted, to all interrupt factors. CONSTITUTION:Interrupt requests I1-I4 generated from input/output ports 1-1- 1-4 are inputted to a register 2 and are transmitted to a priority level giving encoder 4. The encoder 4 transmits an interrupt signal INT to a CPU5 and encodes information having a higher priority level and outputs it as a part of vector information (the first vector information) onto a data bus 6. Input/output ports 1-1-1-4 discriminate whether their own interrupt requests are accepted or not on a basis of the first vector information, and the input/output port whose interrupt request is accepted outputs the second vector information onto the data bus. The CPU5 takes in the first and the second vector information from the data bus 6 and enters into the interrupt processing.
申请公布号 JPS60168240(A) 申请公布日期 1985.08.31
申请号 JP19840023944 申请日期 1984.02.10
申请人 NIPPON DENKI KK 发明人 ETANI MAKOTO
分类号 G06F13/24;G06F9/46;G06F9/48 主分类号 G06F13/24
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