发明名称 DATA PROCESSOR
摘要 PURPOSE:To add a mechanism to read out automatically an address immediately after it is written by storing said written address after detecting that a writing command to a main memory device is delivered. CONSTITUTION:When data are written to a main memory device 2 from a CPU 1 or an input/output controller 4, a memory address 7 is preserved at an address latch 9 by a memory write command signal 8. A sequence circuit 13 sends a bus request signal 10 to a system bus 51 to acquire the bus using right and transmits the address signal of the latch 9. Then a memory read command 15 is sent to the bus 51 and the device 2 executes a reading operation in response to the command 15. At the same time, the device 2 checks the parity of a parity check generating mechanism 3.
申请公布号 JPS61285558(A) 申请公布日期 1986.12.16
申请号 JP19850127367 申请日期 1985.06.12
申请人 MITSUBISHI ELECTRIC CORP 发明人 MORIKAWA SHUHEI
分类号 G06F11/10;G06F11/00;G06F12/16 主分类号 G06F11/10
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