| 摘要 |
PURPOSE:To attain the transfer of data at a high speed by setting two FIFO buffers storing the data of n-bit width respectively in parallel between a host bus of 2n-bit width and a local bus of n-bit width. CONSTITUTION:A multiplexer/demultiplexer 19, an FIFO buffer 17 and a buffer circuit 18 are provided between a host bus 14 and a local bus 12. Thus the DMA transfer is possible with 16-bit and 8-bit widths. The changeover between these two data widths is carried out when the execution is started according to the contents of information written to an input/output controller from a host system. Then it is decided from the information set to a control register 10 whether the DMA transfer of 8 bits or 16 bits should be carried out. Based on this information, a local processor 2 decides the data width and informs it to an FIFO controller 20 before execution of the DMA transfer. Thus the controller 20 works by said information.
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