| 摘要 |
<p>PURPOSE:To prevent jitter in phase from being increased by using an amplitude and a phase of a timing component held when the amplitude of the extracted timing component is a prescribed value or over as a synchronizing signal when the extracted amplitude is a prescribed value or below. CONSTITUTION:The real part AX and the imaginary part AY of a signal being the result from a reception signal from a line subject to filtering, AD conversion, demodulation and AGC processing are fed to a timing extraction section 4 to form an X timing component TX and a Y timing component TY. The vector components of the components TX, TY is operated by an adder 503 of a vector discrimination section 50, compared with a threshold value TH by a comparator 504 and the result is inputted to a polarity discrimination device 505. when the vector component is larger than the value TH, the components TX, TY are sent to a phase hold circuit 5 as outputs XTMR and YTMI. When the component is smaller than the value TH, an output of taps 517, 518 held previously is sent to the circuit 5.</p> |
