| 摘要 |
PURPOSE:To obtain sure counting operation even when a high-speed clock is used and the number of stages of the counter circuits is large by ANDing outputs of plural count circuit connected in cascade and using the result as a carry to prevent the delay time until the carry of each counter circuit is given from being accumulated. CONSTITUTION:The counter circuit 3 is added synchronously with the rising of a clock 2 and a carry 3d is given (from L to H), then a terminal ET 4a of the counter 4 is connected always to the power supply and the EP terminal 5b goes to Hm then the counter circuit 4 is added by the rising of the next clock 2. When the content of the counter circuits 3-7 of each stage reaches 15 (in case of hexadecimal counter), since the ET terminals 3a-7a controlling the carry are connected to the power supply 1, they are in enable-state at all times, then carries 3d-7d are outputted immediately. The carries 3d-7d of each stage are inputted to a NAND gate 8, the output 8e is inputted to a ata input terminal 9f of a flip-flop 9 and a signal removing glitch is obtained from a Q' terminal 9h. |
