| 摘要 |
PURPOSE:To monitor whether plural types of clock pulses are all normal or not by successively detecting plural types of clock pulses obtained by a frequency dividing from a common original oscillator and inspecting the periodicity. CONSTITUTION:A synchronization detecting circuit 1 is constituted of an AND circuit having inputs of clock pulses CL1-CL4. A periodicity inspecting circuit 2 comprises a counter 21 counting an output signal of an original oscillator 3 and a NAND circuit 22 making a carry signal of the counter 21 and a detecting signal of the synchronization detecting circuit inputs. Frequency dividing circuits 411-441 form the clock pulses of various types of cycles and input respectively to counters 45-47. In the counter 21, a least common multiple (ta) of cycles t1-t4 of the clocks CL1-CL4, namely the number of an oscillation of a crystal oscillator 3 in one cycle of the detecting signal of the synchronization detecting circuit 1 in the case of the clock pulse being normal is set beforehand and every time when this set value is counted, the carry signal is generated. The abnormality of the clock pulse is detected by an output signal A of the NAND circuit 22.
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