发明名称 CLOCK GENERATING CIRCUIT
摘要 PURPOSE:To obtain a delay time independently of a power voltage by inserting a depletion transistor (Tr) whose source and gate are connected to a discharge path of an output node of a delay circuit section. CONSTITUTION:The depletion type Tr 18 is provided between the source and common of a Tr 13. In decreasing sufficiently the ON-resistance of the Tr 13 than the Tr 18, a current flowing to the Trs 13, 18 is under control of the current of the Tr 18. Since the gate of the Tr 18 is connected to common together with the source, the Tr 18 is operated always at the saturated region and the flowing current is a constant current. Then the time until the voltage at the output node 23 of a delay circuit section 31A is discharged is inversely proportional to the voltage charged in the output node 23. The switching time of other Trs of the circuit section 31A changes proportionally to the power voltage VCC. Since the two operations are cancelled together, the delay time independently of the voltage VCC is obtained.
申请公布号 JPS61281712(A) 申请公布日期 1986.12.12
申请号 JP19850124665 申请日期 1985.06.07
申请人 NEC CORP 发明人 KATANOSAKA TADAO
分类号 H03K5/135;H03K5/02 主分类号 H03K5/135
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