| 摘要 |
PURPOSE:To obtain an overflow detection circuit in which an overflow signal rises sufficiently even when the bit number of timer count is increased by providing an AND gate outputting an AND signal among the content of latch, the least significant bit and a clock pulse as the overflow signal. CONSTITUTION:When the content of the bit of the least significant digit goes to H, a P-channel transistor (TR) 9a is turned on and a potential at a contact 14a restores H at a point of time T14b and a latch 16 holds a fetched signal Q16 until a point of time T16. A signal Q20 having the same waveform as a conventional waveform is obtained by ANDing an output Q16 of the latch 16, an inverted signal phi' to the input clock phi and a signal Q1 being the content of the bit at the least significant digit. In a conventional circuit, only a half period of that of the clock signal is obtained by descending the potential at the contact 14 to L, but the potential has only to be descended during one period in this circuit and the signal is latched and the AND circuit detects overflow, then it is detected quickly and surely.
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