发明名称 |
Method of optimizing signal timing delays and power consumption in LSI circuits. |
摘要 |
<p>@ A method of optimizing signal timing delays and power consumption through multi-path LSI circuits constructed from a plurality of circuit blocks, each circuit block having associated therewith a plurality of power levels which are selectable to control the timing delays through the circuit block, wherein the method steps include the formation of a power- performance derivative for each circuit block, identifying therefrom the relative contribution to signal delay of the circuit block in the entire multi-path configuration, and selecting the optimum power level for an overall multi-path minimum signal delay condition, through a process of iterative calculation of timing delays through individual circuit blocks and multi-path timing analysis.</p> |
申请公布号 |
EP0204178(A2) |
申请公布日期 |
1986.12.10 |
申请号 |
EP19860106447 |
申请日期 |
1986.05.13 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
LEMBACH, ROBERT FRANCIS;LEWIS, STEVEN DEAN;WILLIAMS, ROBERT RUSSELL |
分类号 |
H03K19/00;G06F17/50;H03K19/0175 |
主分类号 |
H03K19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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