| 摘要 |
PURPOSE:To obtain a system satisfying conditions required as blocked data and capable of conforming changes in an input signal by keeping the format of the blocked data by the address control of a buffer memory and applying block synchronization correction corresponding to the input changes. CONSTITUTION:The timing when data of a read address 0 is outputted from a data output terminal 104 is given by giving 2-clock delay to an output of a counter reset decoder 110 by output clock delay adjusting registers 113, 114. This is used as an output horizontal synchronizing pulse and outputted from a horizontal synchronizing pulse output terminal 115. The vertical synchronizing pulse inputted from the vertical synchronizing pulse input terminal 116 is delayed by output clock delay adjustment registers 117, 118 and outputted in matching wit the timing with the horizontal synchronizing pulse. That is, the input data and the horizontal synchronizing pulse are used as a reference and stored with numbering and the output horizontal synchronizing pulse is generated in matching with read of data 0. |
