发明名称 MEMORY ADDRESS CONTROL CIRCUIT
摘要 PURPOSE:To attain the designation of an address with a specific area of a ROM without increasing the number of transistor elements of a decoder circuit, by providing at least >=1 logical circuit means for input of the control signal and a prescribed bit signal contained in an address signal. CONSTITUTION:When a control signal 11 is equal to 0, the logic levels of output signals 4 and 5 of a program counter 1 are outputted as they are for the outputs of OR circuits 15 and 16. Therefore, the address signal 14 outputted from a decoder circuit 9 is equal to 1 when the output signals 3-5 of the counter 1 are equal to 9 respectively. Thus a user program can be executed. While the outputs of both circuits 15 and 16 are forcibly set to 1 when the signal 11 is equal to 1. Then the address signal 13 sent from the circuit 9 is equal to 1 when the signals 3-5 are equal to 0. Then a special test program 10 can be executed.
申请公布号 JPS61279946(A) 申请公布日期 1986.12.10
申请号 JP19850122229 申请日期 1985.06.05
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 HIKICHI HIROSHI;KAWABATA MICHIAKI
分类号 G06F11/22;G11C8/00 主分类号 G06F11/22
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