| 摘要 |
PURPOSE:To attain the transfer of data with high flexibility by receiving a storage address information on a bus after detecting the coincidence between the bit number part designated by the information on the comparison bit number and the allocation address information for a prescribed part of said storage address information. CONSTITUTION:A memory device 1 is connected to a central processing unit 2 and adaptor devices 3 via a bus 4. An allocation address register 12, a comparison bit number register 11 and an address comparator 10 are provided to the unit 2 and devices 3. A bit train corresponding to the highest four bits of an address of the allocation address area is set to the register 12 in the initialization mode of a system for example. At the same time, two bits for designation of the comparison bit number up to four bits are set to the register 11. Then four bits of the register 12 and the upper four bits of an address bus 13 are connected to the comparator 10. The bits corresponding between both inputs are compared with each other by four pairs of exclusive OR circuits ERO. The output of this comparison is compared with the output of the decoder 20 of the register 11 at a gate part 21. This improves the flexibility for the transmission of data.
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