发明名称 CODE DECODING SYSTEM
摘要 <p>PURPOSE:To prevent an error in a decoded data by detecting a single K-bit not consecutive to J-bit from the reception clock recovery circuit of a a decoder of the differential Manchester code so as to apply re-synchronization. CONSTITUTION:In decoding a signal coded by the differential Manchester code, an input data is separated into 4 states of 'O', '1', 'J', 'K' before coding the differential Manchester code by a changing point detection circuit 13, a shift register 12 setting an input signal by an internal clock and a decoder 15. As the result of separation, the 'K' bit not consecutive to 'J' is detected by a detection circuit 17, then a reception clock is corrected by being retarded by one pulse (a half bit) of the internal clock and the decoder output is sent by using the reception clock. Even when the clock recovery is in error and an error data is sent, it is detected and corrected immediately so as to improve the transmission efficiency of the transmission system clock and the reliability.</p>
申请公布号 JPS61270920(A) 申请公布日期 1986.12.01
申请号 JP19850113493 申请日期 1985.05.27
申请人 FUJITSU LTD 发明人 KITAHARA TAKESHI
分类号 H04L25/49;H03M5/12;H04L7/00;H04L7/027;(IPC1-7):H03M5/12 主分类号 H04L25/49
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