发明名称 CLOCK REPRODUCING CIRCUIT
摘要 <p>PURPOSE:To prevent the omission of a clock at the time of the in-use and standby change-over by detecting the phase difference of the in-use and standby clock inputted to a clock receiving circuit and giving the delaying quantity to correct it to a standby clock. CONSTITUTION:The output of in-use and standby clock receiving circuits 1 and 2 (while the circuit 2 is in-use, the circuit 1 is standby) is inputted through delaying circuits 7-1 and 7-2 to a selector circuit 3. The output of the receiving circuits 1 and 2 is inputted to a phase difference detecting circuit 6, the phase difference is detected, and the delaying quantity corresponding to the quantity is given to the delaying circuit 7-2 (or 7-1) at the standby side. Thus, a selecting device 3 changes over from the in-use clock to the standby clock and even then, the omission of the clock is not generated. A switch 6-1 is always changed over to the standby clock side. Thus, the error ration of the data is improved. The circuit is suitable to the clock circuit of the transporting edge station.</p>
申请公布号 JPS61270938(A) 申请公布日期 1986.12.01
申请号 JP19850113373 申请日期 1985.05.27
申请人 FUJITSU LTD 发明人 OKINO TAKAYUKI;MORIMOTO AKIO;KATO TAKEO
分类号 H04B1/74;H04L1/22;H04L7/00 主分类号 H04B1/74
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