| 摘要 |
PURPOSE:To restrain the latch-yp phenomenon of C-MOS IC due to overvoltage by composing the overvoltage protective circuit utilizing Zener effect on the same circuit board as for the circuit to be protected. CONSTITUTION:For the C-MOS inverter circuit composed of N-MOS 3 and P-MOS 2, a Zener diode for protection is formed on the same circuit board. As the voltage applied to a terminal 1a increases gradually, a diode 6a is energized and a current begins to flow toward a terminal 1b. When the voltage becomes over Zener breakdown voltage VZ, a Zener diode 8a is energized and a current begins to flow toward a terminal 1d. At this time, the layout is made so that the impedance between the Zener diode 8a and the terminal 1d becomes sufficiently small, by which an increase in terminal voltage can be restrained at VZ. If a power voltage VDD increases, a Zener diode 8c stops an increase in voltage at VZ and the latch-up phenomenon caused by overvoltage of the power voltage can be prevented. |
