| 摘要 |
Buffer memory to be interposed between a sending system EM supplying sequential, n-bit data in parallel to a fast system and a receiver system RE receiving this data at a slower rate, characterised in that it includes N separate blocks of memory MA, MB, MC, MD in each of which the write/read operations for each group of n simultaneous data items are shifted by one clock cycle with respect to the neighbouring block, each block taking account only of one group out of N of these data items, and thus having available, for its own cycle of operations, a time equal to N clock HAD cycles, this clock cycle being synchronised with that of the sender EM in a write phase and with that of the receiver RE in a read phase. Application: image memory for a digital camera. <IMAGE>
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