| 摘要 |
The position of an end "1" bit in an input number is detected by applying the inverted bits in parallel to inputs of respective NOR gates (61 to 68), the other inputs of which are connected to the nodes of a chain of dynamic field effect transistors (A1 to A8) along which a "O" is propagated. The coincidence of two O's at the inputs of a NOR gate causes it to produce a "1" output representing the location of the end "1" of the input number. The outputs of the NOR gates (L1 to L8) are connected to the column conductors of an field effect transistor array (LA) which produces on the row conductors array in parallel, inverted, binary coded form a number corresponding to the position of the NOR gate producing a "1" output. The apparatus may be divided into several units (U1 to U4) responsive to adjacent groups of the bits of the input number each producing a representation of the location of the end "1" in its group. The units are coupled together so that a representation from a preceding unit blocks the output of a representation from a subsequent unit. |
