发明名称 DECODING CIRCUIT
摘要 <p>PURPOSE:To make unnecessary to increase a manufacturing process and to secure a large space, and to obtain a ROM having a high reliability, by constituting a high voltage applied part of a P channel type FET. CONSTITUTION:A high voltage applied part 22 having a P channel type FET Q25 in which a control signal C22 is applied to the gate and a P channel type FET Q24 in which a constant-voltage V0 is applied to the gate is provided in series between a selecting gate line X2 and a write voltage VPP line. The signal C22 becomes a VPP level except the time of a write operation, the Q25 becomes off, and an influence from the VPP line to the line X2 is cut off. Also, at the time of write, the signal C22 becomes a ground level, the Q25 becomes on, and if a decoder output D21 is a ground level, the Q22 becomes off, the selecting line X2 rises to the vicinity of the VPP level, and when a high voltage is applied to a digit lie, a cell M21 becomes a write operation state.</p>
申请公布号 JPS61267996(A) 申请公布日期 1986.11.27
申请号 JP19850294271 申请日期 1985.12.25
申请人 NEC CORP 发明人 HIGUCHI MISAO
分类号 G11C17/00;G11C16/06;G11C16/12 主分类号 G11C17/00
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