发明名称 LOGIC DESIGN RULE CHECKING SYSTEM
摘要 PURPOSE:To improve the reliability of a substrate product by adding a simplified simulator to trace the prescribed fixed signal level concerning a basic gate and checking a design standard to change depending upon a signal level. CONSTITUTION:A simplified simulator to simulate from an obvious signal level to a basic gate only such as NAND and AND like a pull-up resistance and an earth is added to a logic design rule checker on a circuit drawing. After a circuit diagram 1 is inputted into a data base 2, the diagram is processed by a simplified simulator 3 and thereafter, processed by a logic design rule checker. Since the design standard of the electronic logical substrate can be checked more correctly, the improvement of the reliability of the electronic logical substrate and the improvement of the efficiency of the electronic logical substrate design can be realized.
申请公布号 JPS61267178(A) 申请公布日期 1986.11.26
申请号 JP19850108146 申请日期 1985.05.22
申请人 HITACHI LTD 发明人 MATSUMOTO NOBUHIKO
分类号 G06F17/50 主分类号 G06F17/50
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