发明名称 DUTY RATIO ADJUSTING CIRCUIT
摘要 PURPOSE:To simplify the constitution and to adjust easily the duty ratio by connecting alternately NAND gates and NOR gates comprising the series connection of serial and parallel connections between power supplies in cascade to change the order or the number of stages. CONSTITUTION:Two NAND gates 2, 4 and two NOR gates 3, 5 are connected alternately in cascade. One input of the NAND gates 2, 4 is connected to a power supply VDD and one input of the NOR gates 3, 5 is connected to a ground potential GND and they act like inverters. In inputting a square wave (a) with 50% duty ratio from an input terminal 1, the fall of an output (b) of the wave delays from the rise through the NAND gate 2 and the duty ratio is decreased by it. Then the rise of an output (c) delays from fall through the NOR gate 3 and the duty ratio is decrease by it. Similarly, the duty ratio of the pulse is decreased as shown in figures (d, e) through the NAND gate 4 and the NOR gate 5.
申请公布号 JPS61265914(A) 申请公布日期 1986.11.25
申请号 JP19850108525 申请日期 1985.05.20
申请人 NEC IC MICROCOMPUT SYST LTD 发明人 KOSUGE NORIHIRO
分类号 H03K5/04;(IPC1-7):H03K5/04 主分类号 H03K5/04
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