| 摘要 |
<p>PURPOSE:To accurately and effectively perform the prevention of zero continuance by adding and sending the number of time of a conversion from continuous '0's to '1's as a conversion number of time bit at the forefront of an information bit and separating the conversion number of time bit from the information bit at a receiving part. CONSTITUTION:A zero continuing number of time N is detected 12 from an input signal by every 16 bits and is sent to a multiplex circuit 14. At the first conversion circuit 11, '0' of a 16th bit is converted to '1' and is inputted to a delay circuit 13 as an information bit S. A delayed information bit S is inputted to a multiplex circuit 14 delaying by a conversion number of time N. The multiplex circuit circuit 14 adds and sends with adding the bit N on the forefront of the bit S. At a receiving side, N+S is separated 21 with separating it to the N and the S and the bits N and S are inputted to a conversion position detecting circuit 22 detecting conversion positions and are inputted to the second conversion circuit 23. At the second conversion circuit 23, '1' is converted to '0' out of the bit S based upon a conversion position information and it is outputted as an original information bit. Thereby, the prevention of the zero continuance is accurately and effectively performed.</p> |
