| 摘要 |
PURPOSE:To decrease the number of gates and to attain a high-speed operation of a CMOS logical circuit with high density by providing a clock gate type inverter circuit to a carry signal output part, a transfer fate type exclusive OR circuit to an addition output part and an exclusive logical OR circuit of a composite gate type to a double signal input part respectively. CONSTITUTION:The input A and B are provided together with the input C of a carry signal, the sum output Qs, the output Qc of the carry signal, the output Qc' showing the NOT of a signal Qc and P and N showing p- and n-type transistors TR. The parts 1 and 2 enclosed by dotted lines show the two types of exclusive OR. An exclusive OR 1 can be formed with 10 pieces of TRs, for example, and an exclusive OR 2 can be formed with 6 pieces of TRs respectively. Thus the highest density is attained. Furthermore a high-speed operation is attained because the number of gates provided between the input and the output of the carry signal is equal to only a single stage of a clock gate type inverter.
|
