发明名称 DECODER CIRCUIT
摘要 <p>PURPOSE:To improve a read characteristic by permitting a pulse generating circuit for inputting a control signal for controlling the programming action of a semiconductor memory element to generate a pulse signal. CONSTITUTION:After a program mode is terminated, a speed discharging an electric charge charged to a selected word line X1 in a program mode will not change due to the variance of the threshold of a shallow depression, and therefore the threshold of the shallow depression can be decided only by the read characteristic. Namely, under a drain of 5V, a gate at zero V and a source at zero V, a current ITD2 flowing into a Q16 can be set to valus where a read voltage VR becomes highest. Thus the voltage of the word line selected in a read mode can be set at a high level to accelerate a speed, and the value of a critical VCC acting normally is set at a low level to improve the read characteristic.</p>
申请公布号 JPS61260494(A) 申请公布日期 1986.11.18
申请号 JP19850101927 申请日期 1985.05.14
申请人 NEC CORP 发明人 HASHIMOTO KIYOKAZU;KASHIMURA MASAHIKO
分类号 G11C17/00;G11C16/06 主分类号 G11C17/00
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