| 摘要 |
PURPOSE:To reduce the generation of step-out by providing the 1st phase comparator which performs the phase comparison having a small fall time difference between a latch circuit and a monostable circuit and the 2nd phase comparator which performs the phase comparison with a large time difference and using the 2nd phase comparator only when a lead pulse is pulled in. CONSTITUTION:The 1st phase comparator consists of a data latch circuit DL11' and a monostable multivibrator MS12'; while the 2nd phase comparator is provided with a circuit DL21 and an MS22. A dividing circuit 23 divides the output of a VCO 14' down to half and this division output 43 resets the DL 21 via a differentiating circuit 24. The output pulse widths of the MS12' and the MS22 are set at about 0.25tau and 0.5tau respectively (tau: bit time). As a result, the comparison widths of the 1st and 2nd phase compartors are equal to 0.5tau and 0.25tau respectively. An AND circuit 25 gates the input of the 1st phase comparator, and an AND-OR circuit 26 switches the input signal of the 2nd phase comparator.
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