| 摘要 |
PURPOSE:To provide general-purpose properties to the shift quantity to obtain a correct intermediate result by holding the carry, which is detected by an auxiliary adder, in the least significant bit of a register if the carry is generated when data are added. CONSTITUTION:The carry output and the sum output of a carry save adder group 30 are held in registers 40 and 50, and outputs of registers 40 and 50 are inputted to shifters 60 and 61, and outputs of shifters 60 and 61 are inputted to the adder group 30 again. If the carry is generated form the most significant digit as the result of addition of shifted-out data when outputs of registers 40 and 50 are added by an adder 80 and the result is shifted right by shifters 60 and 61, this carry is held in the least significant bit of the register 40 as the least significant bit of the carry output of the adder group 30. Thus, data of the carry output and the sum output are shifted out when intermediate results obtained as the carry output and the sum output of the adder group 30 are shifted right by the feedback bus to the input of the group 30, and the carry generated from the most significant digit is stored in the least significant bit of the carry output of the adder 30 as a part of the following intermediate results. |
