| 摘要 |
PURPOSE:To make it possible to monitor the internal state of an LSI system without increasing the number of address signals and the number of pins by connecting status registers in parallel and hierarchically and enabling to transfer the content of each register to an output register through a bus. CONSTITUTION:Among various information indicating internal stage, information that needs the stopping of the system according to error state, and error information necessary for program debugging and a system debugging are stored in an ERR 32. The informations are classified and decoded by a decoder 37 and reflected to an STR 31 together with other information, and the outlines of the state of operation and error can be known by monitoring the STR 31. Detailed error information is stored in the ERR 32, and the ERR 32 is connected with an OR 30 through a bus. On receiving command from a CPU, the ERR 32 transfers the information to the OR 30 once and then reads out. New address signal by the increase of ERR 32 is not necessary and accordingly, it is not necessary to increase the number of pins.
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