发明名称 SIMULATION METHOD FOR LOGIC CIRCUIT
摘要 PURPOSE:To reduce the quantity of necessary memory by providing the signal value storing table of 1 bit per one signal for a read only memory section etc. and providing the signal value storing table of plural bits per one signal for other parts. CONSTITUTION:Signal storing tables 14, 15 correspond to AND gates 21, 22 and their input output signal values 105-107 are expressed by two bits per one signal. A signal value storing table 16 corresponds to a ROM 23 and an area 108 stores an input signal value, an area 109 stores an output signal value and an area 110 stores a signal value stored in the ROM. The storing table 16 allots 2 bits per one signal for an input and output signal value. However, as it is impossible for the content of memory in the area 110 except '0' and '1', it is expressed by 1 bit per one signal. Thus, 8 bits required formerly to store the signal value of 4 bits is reduced to a half, 4 bits.
申请公布号 JPS61248142(A) 申请公布日期 1986.11.05
申请号 JP19850088501 申请日期 1985.04.26
申请人 HITACHI LTD 发明人 TADA OSAMU;MIYOSHI MASAYUKI;KAZAMA YOSHIHARU
分类号 G06F11/25;G06F11/26;G06F17/50 主分类号 G06F11/25
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