发明名称 SYSTEM FOR PREVENTING DIVERGENCE AT REMOTE LOOP
摘要 PURPOSE:To decrease the loop forming time by stopping the operation of an automatic gain control circuit and an automatic equalizer of a MODEM until a USC 1 (unscrambled binary 1) signal is not detected when the MODEM detects the signal in forming a remote loop 2 in the CCITT recommendations V22bis. CONSTITUTION:In forming a loopback loop by a MODEM B, when the USC 1 is detected by a USC 1 detection circuit 30 of the MODEM B, a signal is sent immediately to an automatic gain control circuit (AGC) 12 and an automatic equalizer (AEQ) 18 to stop the operation to stop them at the state just before. Thus, although the adjustment of the AGC, AEQ in a faulty direction is executed at a slight time from the transmission of the USC 1 till its detection, it is intermitted immediately, then no faulty state is caused, and when a MO DEM A sends a scrambled 1 (SCR 1), the MODEM B detects immediately it to form a loop quickly.
申请公布号 JPS61248634(A) 申请公布日期 1986.11.05
申请号 JP19850090092 申请日期 1985.04.26
申请人 FUJITSU LTD 发明人 MIZUTANI YASUNAO;MURATA HIROYASU
分类号 H04B3/04;H04L1/14;H04L1/24;H04L29/14 主分类号 H04B3/04
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