发明名称 Logic circuit with MOSFETs arranged to reduce current flow
摘要 A logic circuit, comprising a plurality of driver MOSFETs and one load MOSFET, produces an output signal responsive to input signals. The driver MOSFETs are each controlled by an input signal and the load MOSFET is controlled by one of input signals to conduct at opposite times to the driver MOSFET controlled by the same input signal. Therefore, a logic circuit with low power consumption and a small area is provided.
申请公布号 US4621207(A) 申请公布日期 1986.11.04
申请号 US19840643713 申请日期 1984.08.24
申请人 KABUSHIKI KAISHA TOSHIBA;TOSHIBA MICRO-COMPUTER ENGINEERING CORP. 发明人 SUGANUMA, KAZUO;HAMAI, TSUNEO
分类号 H03K19/00;H03K19/0948;H03K19/20;(IPC1-7):H03K19/017;H03K19/094 主分类号 H03K19/00
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