| 摘要 |
PURPOSE:To prevent a CPU from being monopolarized with data input/output by providing a detecting circuit of requests to a bus input/output device, a direct memory access DMA request circuit, a DMA response circuit, and an interrupt control circuit. CONSTITUTION:A system control circuit 1 consists of the CPU and a memory. A DMA control circuit 8 detects a bus state signal 14 and a REQ signal 15 from a Sugart associate system interface (SASI) bus input/output device 9 to send a DMA request signal 24 to a DMA controller DMAC 7. The circuit 8 detects a DMA response signal 25 and a read/write signal 26 from the DMAC 7 to send a response signal 21. The circuit 8 reports the end of DMA to the circuit 1 by an interrupt signal 28. Thus, the CPU is prevented from being monopolarized by data input/output.
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