| 摘要 |
PURPOSE:To read or write a desired address more by reducing the number of the refresh having no reading and writing of the memory as less as possible. CONSTITUTION:On respective timings of a count signal, when ROW addresses A2, A1, A0 at that time are stored in either of memory access memory sections 16, 17, a refresh is not carried out. In a timing t4, since a ROW address '111' is not stored in both the memory access memory sections 16, 17, the refresh is carried out. Similarly, in the respective timings of the refresh, the ROW addresses A2, A1, A0 at that time are not stored in both the memory access memory sections 16, 17, but the refresh is carried out. Thereby, the ROW addresses A2, A1, A0 carry out the different memory accesses frequently, in the respective cycles of a cycle TRF, the number of the refresh of a DRAM section 1 according to a refresh request signal 7 becomes smaller than eight times.
|
