| 摘要 |
PURPOSE:To reduce an occupying area, and to increase capacitance by bringing a MOS capacitance to the state, in which an electrode is buried on its midway by utilizing a cross striped groove side-wall, and also bringing a MOS transistor to the state in which the transistor is superposed on a capacitance electrode by using a groove wall and a gate electrode is buried. CONSTITUTION:Cross striped grooves 12 reaching a p<+> type Si substrate 11 are formed to p<-> epitaxial layers 13 on the substrate 11, and coated with PSG and thermally treated, thus shaping n<-> layers 16 and thermal oxide films 14. The grooves are buried with poly Si 15 and the surface is etched from flat surfaces, and the poly Si capacitance electrodes 15 are left on groove bottoms. Oxide films 14 are removed, and the surface is coated with BSG and thermally treated, thus shaping p<-> channels 19 for a FET. Gate oxide films 17 and poly Si 18 are superposed, and poly Si gate electrodes (word lines) 18 are formed while surrounding p<-> islands 13 on side walls on the electrodes 15 through RIE. As ions are implanted to shape n<+> drains 20 on the top surfaces of each island, CVD oxide films 21 are deposited, and openings are bored and Al bit wirings 22 are formed and connected to drains for cells in the lateral direction. According to the constitution, a memory device having a small cell area and sufficient capacitance is acquired. |
