| 摘要 |
PURPOSE:To enable the adjustment of a system delay, by correcting the system delay with the adjustment of multi-phase clocks to bring the results of the comparison between data to be measured and an expected value into a memory along with a pattern data and an address data. CONSTITUTION:A multi-phase clock generation circuit 61 receives a system base clock CLK to generate a multi-phase clock by delaying the base clock properly. A group 62 of delay latches with the delay value adjustable is made up of a group of multi-stage delay latches, for instance, to latch address data and pattern data at the timing of a clock C1, shifted to the latching at the next stage by a clock C2 and finally, it is latched by a clock C3. Thus, address data and pattern data can be sent from the time of the clock C1 to the time of the clock C3 to output. The latch data at the final stage is taken into a latch 63 at the timing of the clock C4. The results of comparison are inputted into a latch 66 from a timing module of the clock C4. |
