| 摘要 |
PURPOSE:To read the data which are supplied from all digital signal input modules at an equal time point by setting the timing to hold the input signal at an input holding register independently of the timing to output the input signal to an output bus line. CONSTITUTION:The digital signal supplied from outside via an input lien is rectified through an input resistance part 1 and a rectifying part 2 and applied to a photocoupler 3 for insulation. The noises are deleted through a filter 4 for the output of the coupler 3. Then the output of the coupler 3 is supplied to an input holding register 9. This register 9 holds data by the timing signal 11 of a free bus line P1 used for the automatic measurement of an electronic computer and for the data way of a control CAMAC system. The held signal is delivered by a data read register 5 and a data read gate 6 through read bus lines R1-R24 with the timing of function codes F(0) and A(0) of the data way. While the output of the register 9 is sent to diodes 82a and 82b via current limiting resistances 81a and 81b of a display part 8. |
