| 摘要 |
PURPOSE:To obtain a timing generating circuit whose operation is made stable by using a latch circuit so as to latch an output signal of a delay element by means of a timing signal based on an original timing signal and controlling the delay time of the delay element of a delay circuit based on the output signal of the latch circuit. CONSTITUTION:A control signal generating circuit 20 generates a control signal based on output signals A, B of latch circuits 16, 18 and outputs them to delay elements 121-1211. When the output signals A, B are logical '0', '1' respectively, a control signal keeping the delay time of the delay elements 121-1211 is outputted, and when the output signals A, B are logical '1' respectively, a control signal decreasing the delay time is outputted, and when the output signals A, B are logical '0' respectively, a control signal prolonging the delay time is outputted. Then, the delay time of the delay elements 121-1211 is controlled to 1/10 of the period T of the original clock signal phiL. Thus, an accurate and optional timing signal is generated by using output signals phi1-phi11 of the delay elements 121-1211. |
