| 摘要 |
<p>1. A selectively accessible memory (RAM) having an active load for storing binary information and comprising a plurality of cells organized in lines and columns, each cell comprising a first and a second transistor of the NPN type each comprising on the one hand a first and a second emitter, the first emitters being connected to each other and the second emitters being each connected to a column selection conductor, and on the other hand a base connected to the collectors of a third and a fourth transistor, respectively, of the PNP type, and finally a collector connected to the bases of the third and the fourth transistor, respectively, the collector of the third transistor being connected to the base of the fourth transistor and conversely, while the emitters of the third and fourth transistors are connected to each other and to a line selection conductor and comprise a diode (D1, D2) in parallel to the emitter-base junction of the third (T3a, T3b, ...) and fourth (T4a, T4b, ...) transistors of each cell and having the same direction as the said junction, characterized in that, in order to reduce the inverse current of the non-selected cells, the said diode (D1, D2) is formed by the collector-base junction of a shunt transistor (T5b, T6b) of the NPN type whose emitter and base ar mutually short-circuited and connected to the said line selection conductor.</p> |
