| 摘要 |
<p>PURPOSE:To extract stably a data and a clock signal by making a pulse signal generated by a transition detecting means ineffective while the 1st mask signal is logical '0'. CONSTITUTION:A counter 21 counts a clock signal CLK to generate signals MS and DCLK, the signal MS outputted from the 1st mask signal output terminal is kept to logical '1' until an input is given to the clear terminal and cleared to logical '0' when a sampling signal SP is inputted. The value M is set as N/2<M<N, a pulse signal EP generated by an edge detection circuit 22 is outputted from an AND gate 23 as the signal SP at the counts N after the signal SP is generated and a pulse train of the N periods is obtained. The signal DCLK cleared to logical '0' by the signal SP and reaching logical '1' after the counts P (0<P<M) where the data is made stable becomes a clock signal representing the stability of the DATA. Thus, the data and clock signal are extracted stably.</p> |
