发明名称 STORE BUFFER CONTROL SYSTEM
摘要 PURPOSE:To improve the throughput of write to a main storage by reading out a buffer to be written to the main storage and the next buffer at the same time, and completing an access to the main storage by once, when the higher ranks of main storage addresses of both said buffers have coincided with each other. CONSTITUTION:A data bus width for write to a main storage is set to two times of a data width of an internal buffer of a store buffer 10, and the internal buffer 2 is constituted of a 2 port RAM 21. A buffer to be written to the main storage and the next buffer are read out at the same time, and when the higher ranks of main storage addresses of both the buffers have coincided with each other, an access to the main storage is completed by once by a swap of both data. In this way, the throughput of write to the main storage of the internal buffer of the store buffer can be raised.
申请公布号 JPS61223956(A) 申请公布日期 1986.10.04
申请号 JP19850063654 申请日期 1985.03.29
申请人 HITACHI LTD 发明人 MIYAZAKI YOSHIHIRO;TANJI MASAYUKI;MORIOKA MICHIO
分类号 G06F12/08 主分类号 G06F12/08
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